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Allwinner /D1H /TWI[1] /TWI_LCR

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Interpret as TWI_LCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)sda_ctl_en 0 (low)sda_ctl 0 (disable)scl_ctl_en 0 (low)scl_ctl 0 (low)sda_state 0 (low)scl_state

scl_state=low, scl_ctl=low, sda_state=low, sda_ctl=low, scl_ctl_en=disable, sda_ctl_en=disable

Description

TWI Line Control Register

Fields

sda_ctl_en

TWI_SDA Line State Control Enable

0 (disable): undefined

1 (enable): undefined
sda_ctl

TWI_SDA Line State Control Bit

0 (low): undefined

1 (high): undefined
scl_ctl_en

TWI_SCL Line State Control Enable

0 (disable): undefined

1 (enable): undefined
scl_ctl

TWI_SCL Line State Control Bit

0 (low): undefined

1 (high): undefined
sda_state

Current State of TWI_SDA

0 (low): undefined

1 (high): undefined
scl_state

Current State of TWI_SCL

0 (low): undefined

1 (high): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data